The operations of addition and multiplication utilizing Galois field (GF) arithmetic are very different from the usual multiply and add instructions in digital signal processors (DSPs). Specialized instructions are therefore typically needed to perform the computations in a reasonable amount of time. The specialized instructions specify the inputs, the result destination and the type of GF operation to be executed. A GF multiplication operation of two input elements is an important function which signal processing units and DSPs may need to perform. In considering GF operations, there are at least two different ways to encode the elements of a GF: 1) using the polynomial coefficients as a vector of bits, or 2) using the exponent form. Both of these two encodings make the calculation of one of the operations easy, but the other more complex to calculate. For example, the GF addition in utilizing the polynomial coefficients approach is an exclusive or (XOR), while a multiplication of two elements in exponent form is an addition of the exponents. However, the multiplication operation, utilizing the polynomial coefficient form, and, the addition operation, utilizing the exponent form, are typically both more complex to implement.
Further details of several prior art approaches are found in the following patents: “Galois Field Computer,” U.S. Pat. No. 4,162,480, “Multiplier in a Galois Field,” U.S. Pat. No. 4,918,638, and “Galois Field Arithmetic Apparatus and Method,” U.S. Pat. No. 6,134,572. The first patent describes a table lookup for the GF multiplication of GF(25). The second patent uses two function stages to calculate a GF multiplication utilizing a binary multiplier array for a first function stage and a polynomial reducer for the second function stage. The third patent uses the exponent representation form.